View 80960JD-50_4520424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, includin g infringement of any patent or copyright, for sale and use of intel products except as provided in intel?s terms and conditions of sale for such prod ucts. information contained herein supersedes previously published specifications on these devices from intel . ? intel corporation, 1995 september 199 5 order number: 272596-00 2 a preliminar y 80960j d embedded 32-bit microprocesso r figure 1. 80960j d microprocesso r n pin/code compatible with all 80960jx processor s n high-performance embedded architectur e ? one instruction/clock executio n ? core clock rate is 2x the bus cloc k ? load/store programming mode l ? sixteen 32-bit global register s ? sixteen 32-bit local registers (8 sets ) ? nine addressing mode s ? user/supervisor protection mode l n two-way set associative instruction cach e ? 80960jd - 4 kbyt e ? programmable cache locking mechanis m n direct mapped data cach e ? 80960jd - 2 kbyt e ? write through operatio n n on-chip stack frame cach e ? seven register sets can be save d ? automatic allocation on call/retur n ? 0-7 frames reserved for high-priority interrupt s n on-chip data ra m ? 1 kbyte critical variable storag e ? single-cycle acces s n high bandwidth burst bu s ? 32-bit multiplexed address/dat a ? programmable memory configuratio n ? selectable 8-, 16-, 32-bit bus width s ? supports unaligned accesse s ? big or little endian byte orderin g n new instruction s ? conditional add, subtract and selec t ? processor managemen t n high-speed interrupt controlle r ? 31 programmable prioritie s ? eight maskable pins plus nm i ? up to 240 vectors in expanded mod e n two on-chip timer s ? independent 32-bit counting ? clock prescaling by 1, 2, 4 or 8 ? lnternal interrupt source s n halt mode for low powe r n ieee 1149.1 (jtag) boundary scan compatibilit y n package s ? 132-lead pin grid array (pga ) ? 132-lead plastic quad flat pack (pqfp ) pin 1 132 99 66 33 i96 0 ? i m i ? 19xx m ? 19xx a a8 0 960 j d ng8 0 960 j d xxxxxxxxa 2 xxxxxxxxa 2
preliminar y i i a 80960j d 80960jd embedded 32-bit microprocesso r 1.0 purpose ................................................................................................................................ .................. 1 2.0 80960j d overview ................................................................................................................................ . 1 2.1 80960 processor core ........................................................................................................................ 2 2.2 burst bus ................................................................................................................................ ............ 2 2.3 timer unit ................................................................................................................................ ........... 3 2.4 priority interrupt controller ................................................................................................................. 3 2.5 instruction set summary .................................................................................................................... 3 2.6 faults and debugging ......................................................................................................................... 3 2.7 low power operation ......................................................................................................................... 4 2.8 test features ................................................................................................................................ ...... 4 2.9 memory-mapped control registers .................................................................................................... 4 2.10 data types and memory addressing modes .................................................................................... 4 3.0 package information ........................................................................................................................ 6 3.1 pin descriptions ................................................................................................................................ .. 6 3.1.1 functional pin definitions ........................................................................................................ 6 3.1.2 80960j x 132-lead pga pinout ............................................................................................. 1 3 3.1.3 80960j x pqfp pinout ........................................................................................................... 1 7 3.2 package thermal specifications ...................................................................................................... 2 0 3.3 thermal management accessories .................................................................................................. 2 2 4.0 e lectrical specifications ............................................................................................................ 2 3 4.1 absolute maximum ratings .............................................................................................................. 2 3 4.2 operating conditions ........................................................................................................................ 2 3 4.3 connection recommendations ......................................................................................................... 2 4 4.4 dc specifications ............................................................................................................................. 2 4 4.5 ac specifications .............................................................................................................................. 2 6 4.5.1 ac test conditions and derating curves ............................................................................... 3 3 4.5.2 ac timing waveforms ............................................................................................................ 3 4 5.0 bus functional waveforms ......................................................................................................... 4 2 6.0 device identification ....................................................................................................................... 5 6 7.0 revision history ............................................................................................................................... 5 6
ii i preliminar y 80960j d a figure s figure 1. 80960jd microprocessor ........................................................................................................... 0 figure 2. 80960jd block diagram ............................................................................................................ 2 figure 3. 132-lead pin grid array bottom view - pins facing up .......................................................... 1 3 figure 4. 132-lead pin grid array top view - pins facing down ........................................................... 1 4 figure 5. 132-lead pqfp - top view ..................................................................................................... 1 7 figure 6. 50 mhz maximum allowable ambient temperature ................................................................ 2 1 figure 7. 40 mhz maximum allowable ambient temperature ................................................................ 2 2 figure 8. ac test load ............................................................................................................................ 3 3 figure 9. output delay or hold vs. load capacitance ............................................................................ 3 3 figure 10. rise and fall time derating ..................................................................................................... 3 4 figure 11. clkin waveform ..................................................................................................................... 3 4 figure 12. output delay waveform for t ov1 ............................................................................................. 3 5 figure 13. output float waveform for t o f ................................................................................................ 3 5 figure 14. input setup and hold waveform for t is 1 and t ih 1 ................................................................... 3 6 figure 15. input setup and hold waveform for t is 2 and t ih 2 ................................................................... 3 6 figure 16. input setup and hold waveform for t is 3 and t ih3 ................................................................... 3 7 figure 17. input setup and hold waveform for t is 4 and t ih 4 ................................................................... 3 7 figure 18. relative timings waveform for t lx l and t lxa ......................................................................... 3 8 figure 19. dt / r and de n timings waveform .......................................................................................... 3 8 figure 20. tck waveform ......................................................................................................................... 3 9 figure 21. input setup and hold waveforms for t bsis 1 and t bsih 1 ......................................................... 3 9 figure 22. output delay and output float waveform for t bsov 1 an d t bsof 1 .......................................... 4 0 figure 23. output delay and output float waveform for t bsov 2 and t bsof 2 .......................................... 4 0 figure 24. input setup and hold waveform for t bsis 2 and t bsih 2 ........................................................... 4 1 figure 25. non-burst read and write transactions without wait states, 32-bit bus ............................... 4 2 figure 26. burst read and write transactions without wait states, 32-bit bus ...................................... 4 3 figure 27. burst write transactions with 2,1,1,1 wait states, 32-bit bus ................................................ 4 4 figure 28. burst read and write transactions without wait states, 8-bit bus ........................................ 4 5 figure 29. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bus ................................................................................... 4 6 figure 30. bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian ........................... 4 7 figure 31. hold/holda waveform for bus arbitration .......................................................................... 4 8 figure 32. cold reset waveform .............................................................................................................. 4 9 figure 33. warm reset waveform ............................................................................................................ 5 0 figure 34. entering the once state ......................................................................................................... 5 1 figure 35. summary of aligned and unaligned accesses (32-bit bus) .................................................... 5 4 figure 36. summary of aligned and unaligned accesses (32-bit bus) (continued) ................................ 5 5
preliminar y i v a 80960j d table s table 1. 80960jx instruction set ................................................................................................................ 5 table 2. pin description nomenclature ...................................................................................................... 6 table 3. pin description ? external bus signals ...................................................................................... 7 table 4. pin description ? processor control signals, test signals and power ..................................... 1 0 table 5. pin description ? interrupt unit signals .................................................................................... 1 2 table 6. 132-lead pga pinout ? in signal order ................................................................................... 1 5 table 7. 132-lead pga pinout ? in pin order ....................................................................................... 1 6 table 8. 132-lead pqfp pinout ? in signal order ................................................................................ 1 8 table 9. 132-lead pqfp pinout ? in pin order ..................................................................................... 1 9 table 10. 132-lead pga package thermal characteristics ...................................................................... 2 0 table 11. 132-lead pqfp package thermal characteristics ................................................................... 2 1 table 12. 80960j d operating conditions .................................................................................................. 2 3 table 13. 80960j d dc characteristics ...................................................................................................... 2 4 table 14. 80960jd i c c characteristics ...................................................................................................... 2 5 table 15. 80960j d ac characteristics (50 mhz) ...................................................................................... 2 6 table 16. note definitions for table 15, 80960jd ac characteristics (50 mhz) ...................................... 2 8 table 17. 80960j d ac characteristics (40 mhz) ...................................................................................... 2 8 table 18. 80960j d ac characteristics (33 mhz) ...................................................................................... 3 1 table 19. natural boundaries for load and store accesses ..................................................................... 5 2 table 20. summary of byte load and store accesses .............................................................................. 5 2 table 21. summary of short word load and store accesses ................................................................... 5 2 table 22. summary of n -word load and store accesses ( n = 1, 2, 3, 4) .................................................. 5 3 table 23. 80960j d die and stepping reference ....................................................................................... 5 6 table 24. data sheet version -001 to -002 revision history ..................................................................... 5 6
a 80960j d preliminar y 1 1.0 purpos e this document contains advance information for the 80960j d microprocessor, including electrical characteristics and package pinout information. detailed functional descriptions ? other than parametric performance ? are published in the i96 0 ? jx microprocessor user?s guide (272483 ) . throughout this data sheet, references to ? 80960j x ? indicate features which apply to all of the following : ? 80960j a ? 5v, 2 kbyte instruction cache, 1 kbyte data cach e ? 80960j f ? 5v, 4 kbyte instruction cache, 2 kbyte data cach e ? 80960j d ? 5v, 4 kbyte instruction cache, 2 kbyte data cache and clock doublin g ? 80l960j a ? 3. 3 v version of the 80960j a ? 80l960j f ? 3. 3 v version of the 80960j f 2.0 80960j d overvie w the 80960j d offers high performance to cost- sensitive 32-bit embedded applications. the 80960j d is object code compatible with the 80960 core architecture and is capable of sustained execution at the rate of one instruction per clock. this processor?s features include generous instruction cache, data cache and data ram. it also boasts a fast interrupt mechanism, dual progra m - mable timer units and new instructions . the 80960j d ?s clock doubler operates the processor core at twice the bus clock rate to improve execution performance without increasing the complexity of board designs . memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. the 80960j d integrates considerable storage resources on-chip to decouple cpu execution from the external bus . the 80960j d rapidly allocates and deallocates local register sets during context switches. the processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. a 32-bit multiplexed burst bus provides a high-speed interface to system memory and i/o. a full complement of control signals simplifies the connection of the 80960j d to external components. the user programs physical and logical memory attributes through memory-mapped control registers (mmrs) ? an extension not found on the i960 kx, sx or cx processors. physical and logical config u - ration registers enable the processor to operate with all combinations of bus width and data object alignment. the processor supports a homogeneous byte ordering model . this processor integrates two important peripherals: a timer unit and an interrupt controller. these and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar 80960 architecture . the timer unit (tu) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. these operate in either single-shot or auto-reload mode and can generate interrupts. th e interrupt controller unit (icu) provides a flexible means for requesting interrupts . the icu provides full programmability of up to 240 interrupt sources into 31 priority levels. the icu takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. clock doubling reduces interrupt latency by 40% compared to the 80960ja/jf . local registers may be dedicated to high-priority interrupts to further reduce latency. acting independently from the core, the icu compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. the icu also supports the integrated timer interrupts . the 80960j d features a halt mode designed to support applications where low power consumption is critical. the hal t instruction shuts down instruction execution, resulting in a power savings of up to 90 percent . the 80960j d ?s testability features, including once (on-circuit emulation) mode and boundary scan (jtag), provide a powerful environment for design debug and fault diagnosis . the solutions960 ? program features a wide variety of development tools which support the i960 processor family. many of these tools are developed by partner companies; some are developed by intel, such as profile-driven optimizing compilers. for more information on these products, contact your local intel representative .
2 preliminar y 80960j d a figure 2. 80960j d block diagra m programmable bus control unit interrupt controller control address/ instruction sequencer physical region configuration interrupt port 1 k byt e data ram memory interface execution multiply unit divide unit memory-mapped register interface data bus global / local register file src2 dest src1 address control effective constants generation unit address 32-bit address 32-bit data bus request queues and two 32-bit timers 8-set local register cache s r c 1 s r c 2 d e s t pll, clocks, power mgmt boundary scan controller tap 5 clkin 128 s r c 1 s r c 2 d e s t s r c 1 d e s t 9 32 32-bit buses address / data 3 independent 32-bit src1, src2, and dest buses 21 4 kbyte instruction cache two-way set associativ e 2 kbyte direct mapped data cach e 2.1 80960 processor cor e the 80960jx family is a scalar implementation of the 80960 core architecture. intel designed this processor core as a very high performance device that is also cost-effective. factors that contribute to the core?s performance include : ? core operates at twice the bus speed (80960jd only ) ? single-clock execution of most instruction s ? independent multiply/divide uni t ? efficient instruction pipeline minimizes pipeline break latenc y ? register and resource scoreboarding allow overlapped instruction executio n ? 128-bit register bus speeds local register cachin g ? 4 kbyte t wo-way set associative, integrated instruction cach e ? 2 kbyte d irect-mapped, integrated data cach e ? 1 kbyte integrated data ram delivers zero wait state program dat a 2.2 burst bu s a 32-bit high-performance bus controller interfaces the 80960j d to external memory and peripherals. the bcu fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. the external address/data bus is multiplexed .
a 80960j d preliminar y 3 users may configure the 80960j d ?s bus controller to match an application?s fundamental memory organ i - zation. physical bus width is register-programmed for up to eight regions. byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. the bcu?s features include : ? multiplexed external bus to minimize pin coun t ? 32-, 16- and 8-bit bus widths to simplify i/o interface s ? external ready control for address-to-data, data-to- data and data-to-next-address wait state type s ? support for big or little endian byte ordering to facilitate the porting of existing program cod e ? unaligned bus accesses performed transparentl y ? three-deep load/store queue to decouple the bus from the cor e upon reset, the 80960j d conducts an internal self test. then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (ibr) . the user may examine the contents of the caches at any time by executing special cache control instru c - tions . 2.3 timer uni t the timer unit (tu) contains two independent 32-bit timers which are capable of counting at several clock rates and generating interrupts. each is programmed by use of the tu registers. these memory-mapped registers are addressable on 32-bit boundaries. the timers have a single-shot mode and auto-reload capabilities for continuous operation. each timer has an independent interrupt request to the 80960j d ?s interrupt controller. the tu can generate a fault when unauthorized writes from user mode are detected. clock prescaling is supported . 2.4 priority interrupt controlle r a programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. the interrupt unit (iu) also accepts interrupts from the two on-chip timer channels and a single non-maskable interrupt ( nm i ) pin. interrupts are serviced according to their priority levels relative to the current process priority . low interrupt latency is critical to many embedded applications. as part of its highly flexible interrupt mechanism, the 80960j d exploits several techniques to minimize latency : ? interrupt vectors and interrupt handler routines can be reserved on-chi p ? register frames for high-priority interrupt handlers can be cached on-chi p ? the interrupt stack can be placed in cacheable memory spac e ? interrupt microcode executes at twice the bus frequenc y 2.5 instruction set summar y the 80960j x adds several new instructions to the i960 core architecture. the new instructions are : ? conditional mov e ? conditional ad d ? conditional subtrac t ? byte swa p ? hal t ? cache contro l ? interrupt contro l table 1 identifies the instructions that the 80960jx supports. refer to i96 0 ? jx microprocessor user?s guide (272483 ) for a detailed description of each instruction. 2.6 faults and debuggin g the 80960j x employs a comprehensive fault model. the processor responds to faults by making implicit calls to a fault handling routine. specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately . the processor also has built-in debug capabilities. in software, the 80960j x may be configured to detect as many as seven different trace event types. alte r -
80960j d a 4 preliminar y natively, mar k and fmar k instructions can generate trace events explicitly in the instruction stream. hardware breakpoint registers are also available to trap on execution and data addresses . 2.7 low power operatio n intel fabricates the 80960j x using an advanced sub- micron manufacturing process. the processor?s sub- micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. the processor also uses dynamic power management to turn off clocks to unused circuits . users may program the 80960j x to enter halt mode for maximum power savings. in halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. processor execution resumes from internally or externally generated interrupts . 2.8 test feature s the 80960j x incorporates numerous features which enhance the user?s ability to test both the processor and the system to which it is attached. these features include once (on-circuit emulation) mode and boundary scan (jtag) . the 80960j x provides testability features compatible with ieee standard test access port and boundary scan architecture (ieee std. 1149.1). one of the boundary scan instructions, highz, forces the processor to float all its output pins (once mode). once mode can also be initiated at reset without using the boundary scan mechanism . once mode is useful for board-level testing. this feature allows a mounted 80960j d to electrically ?remove? itself from a circuit board. this allows for system-level testing where a remote tester ? such as an in-circuit emulator ? can exercise the processor system . the provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board . the jtag boundary scan feature is an attractive alternative to conventional ?bed-of-nails? testing. it can examine connections which might otherwise be inaccessible to a test system . 2.9 memory-mapped control register s the 80960j d , though compliant with i960 series processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 kx, sx or cx processors. these give software the interface to easily read and modify internal control registers. each of these registers is accessed as a memory- mapped, 32-bit register. access is accomplished through regular memory-format instructions. the processor ensures that these accesses do not generate external bus cycles . 2.10 data types and memory addressing mode s as with all i960 family processors, the 80960jx instruction set supports several data types and formats : ? bi t ? bit field s ? integer (8-, 16-, 32-, 64-bit ) ? ordinal (8-, 16-, 32-, 64-bit unsigned integers ) ? triple word (96 bits ) ? quad word (128 bits ) the 80960j x provides a full set of addressing modes for c and assembly programming : ? two absolute mode s ? five register indirect modes ? index with displacemen t ? ip with displacemen t
preliminar y 5 a 80960j d table 1. 80960j x instruction se t data movemen t arithmeti c logica l bit, bit field and byt e loa d stor e mov e *conditional selec t load addres s ad d subtrac t multipl y divid e remainde r modul o shif t extended shif t extended multipl y extended divid e add with carr y subtract with carr y *conditional ad d *conditional subtrac t rotat e an d not an d and no t o r exclusive o r not o r or no t no r exclusive no r no t nan d set bi t clear bi t not bi t alter bi t scan for bi t span over bi t extrac t modif y scan byte for equa l *byte swa p compariso n branc h call/retur n faul t compar e conditional compar e compare and incremen t compare and decremen t test condition cod e check bi t unconditional branc h conditional branc h compare and branc h cal l call extende d call syste m retur n branch and lin k conditional faul t synchronize fault s debu g processor managemen t atomi c modify trace control s mar k force mar k flush local register s modify arithmetic control s modify process control s *hal t system contro l *cache contro l *interrupt contro l atomic ad d atomic modif y note: asterisk (*) denotes new 80960jx instructions unavailable on 80960ca/cf, 80960ka/kb and 80960sa/sb impl e - mentations .
80960j d a 6 preliminar y 3.0 package informatio n the 80960j d is offered in several speed and package types. the 132-pin pin grid array (pga) device will be specified for operation at v c c = 5. 0 v 5% over a case temperature range of 0 to 8 5 c : ? a80960JD-50 (50 mhz core, 25 mhz bus ) the 132-pin pin grid array (pga) device will be specified for operation at v c c = 5. 0 v 5% over a case temperature range of 0 to 10 0 c : ? a80960jd-40 (40 mhz core, 20 mhz bus ) ? a80960jd-33 (33.33 mhz core, 16.67 mhz bus ) the 132-pin plastic quad flatpack (pqfp) devices will be specified for operation at v c c = 5. 0 v 5% over a case temperature range of 0 to 100c : ? n g 80960j d -40 (40 mhz core, 20 mhz bus ) ? n g 80960j d -33 (33.33 mhz core, 16.67 mhz bus ) for complete package specifications and info r - mation, refer to intel?s packaging handbook (240800) . 3.1 pin description s this section describes the pins for the 80960j d in the 132-pin ceramic pin grid array (pga) package and 132-lead plastic quad flatpack package (pqfp) . section 3.1.1, functional pin definitions describes pin function; section 3.1.2, 80960jx 132- lead pga pinou t and section 3.1.3, 80960jx pqfp pinou t define the signal and pin locations for the supported package types. 3.1.1 functional pin definition s table 2 presents the legend for interpreting the pin descriptions which follow. pins associated with the bus interface are described in table 3. pins associated with basic control and test functions are described in table 4. pins associated with the interrupt unit are described in table 5 . table 2. pin description nomenclatur e symbo l descriptio n i input pin only . o output pin only . i/ o pin can be either an input or output . ? pin must be connected as described . s synchronous. inputs must meet setup and hold times relative to clkin for proper operation . s(e) edge sensitive input s(l) level sensitive inpu t a (... ) asynchronous. inputs may be asynchronous relative to clkin . a(e) edge sensitive input a(l) level sensitive inpu t r (... ) while the processor?s rese t pin is asserted, the pin : r(1) is driven to v cc r(0) is driven to v ss r(q) is a valid output r(x) is driven to unknown state r(h) is pulled up to v c c h (... ) while the processor is in the hold state, the pin : h(1) is driven to v cc h(0) is driven to v ss h(q) maintains previous state or continues to be a valid output h(z) float s p (... ) while the processor is halted, the pin : p(1) is driven to v cc p(0) is driven to v ss p(q) maintains previous state or continues to be a valid outpu t
preliminar y 7 a 80960j d table 3. pin description ? external bus signal s (sheet 1 of 4 ) nam e typ e descriptio n ad31: 0 i/o s(l) r(x) h(z) p(q ) address / data bu s carries 32-bit physical addresses and 8-, 16- or 32-bit data to and from memory. during an address ( t a ) cycle, bits 31:2 contain a physical word address (bits 0-1 indicate size; see below). during a data ( t d ) cycle, read or write data is present on one or more contiguous bytes, comprising ad31:24, ad23:16, ad15:8 and ad7:0. during write operations, unused pins are driven to determinate values . size, which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data transfers during the bus transaction . ad1 ad0 bus transfer s 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfer s when the processor enters halt mode, if the previous bus operation was a : ? write ? ad31:2 are driven with the last data value on the ad bus . ? read ? ad31:4 are driven with the last address value on the ad bus; ad3:2 are driven with the value of a3:2 from the last data cycle . typically, ad1:0 reflect the size information of the last bus transaction (either instruction fetch or load/store) that was executed before entering halt mode . al e o r(0) h(z) p(0 ) address latch enabl e indicates the transfer of a physical address. al e is asserted during a t a cycle and deasserted before the beginning of the t d state. it is active high and floats to a high impedance state during a hold cycle ( t h ) . al e o r(1) h(z) p(1 ) address latch enabl e indicates the transfer of a physical address. al e is the inverted version of ale. this signal gives the 80960j d a high degree of compatibility with existing 80960kx systems . ad s o r(1) h(z) p(1 ) address strobe indicates a valid address and the start of a new bus access. the processor asserts ad s for the entire t a cycle. external bus control logic typically samples ad s at the end of the cycle . a3: 2 o r(x) h(z) p(q ) address3: 2 comprise a partial demultiplexed address bus. 32-bit memory accesses : the processor asserts address bits a3:2 during t a . the partial word address increments with each assertion of rdyrc v during a burst . 16-bit memory accesses : the processor asserts address bits a3:1 during t a with a1 driven on th e be 1 pin. the partial short word address increments with each assertion of rdyrc v during a burst . 8-bit memory accesses: the processor asserts address bits a3:0 during t a , with a1:0 driven on be1: 0 . the partial byte address increments with each assertion of rdyrc v during a burst .
8 preliminar y 80960j d a be3: 0 o r(1) h(z) p(1 ) byte enable s select which of up to four data bytes on the bus participate in the current bus access. byte enable encoding is dependent on the bus width of the memory region accessed : 32-bit bus : be 3 enables data on ad31:24 be 2 enables data on ad23:16 be 1 enables data on ad15:8 be 0 enables data on ad7: 0 16-bit bus : be 3 becomes byte high enable (enables data on ad15:8) be 2 is not used (state is high) be 1 becomes address bit 1 (a1) be 0 becomes byte low enable (enables data on ad7:0 ) 8-bit bus : be 3 is not used (state is high) be 2 is not used (state is high) be 1 becomes address bit 1 (a1) be 0 becomes address bit 0 (a0 ) the processor asserts byte enables, byte high enable and byte low enable during t a . since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst. they remain active through the last t d cycle. for accesses to 8- and 16-bit memory, the processor asserts the address bits in conjunction with a3:2 described above . width/ hltd1: 0 o r(0) h(z) p(1 ) width/halted signals denote the physical memory attributes for a bus transaction : width/hltd1 width/hltd 0 0 0 8 bits wide 0 1 16 bits wide 1 0 32 bits wide 1 1 processor halte d the processor floats the width/hltd pins whenever it relinquishes the bus in response to a hold request, regardless of prior operating state . d / c o r(x) h(z) p(q ) data/cod e indicates that a bus access is a data access (1) or an instruction access (0). d / c has the same timing as w / r . 0 = instruction access 1 = data acces s w / r o r(0) h(z) p(q ) write/rea d specifies, during a t a cycle, whether the operation is a write (1) or read (0). it is latched on-chip and remains valid during t d cycles . 0 = read 1 = write table 3. pin description ? external bus signal s (sheet 2 of 4 ) nam e typ e descriptio n
preliminar y 9 a 80960j d dt / r o r(0) h(z) p(q ) data transmit / receiv e indicates the direction of data transfer to and from the address/data bus. it is low during t a and t w / t d cycles for a read; it is high during t a and t w / t d cycles for a write. dt / r never changes state when de n is asserted . 0 = receive 1 = transmi t de n o r(1) h(z) p(1 ) data enabl e indicates data transfer cycles during a bus access. de n is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. de n is used with dt / r to provide control for data transceivers connected to the data bus . 0 = data cycle 1 = not data cycl e blas t o r(1) h(z) p(1 ) burst las t indicates the last transfer in a bus access. blas t is asserted in the last data transfer of burst and non-burst accesses. blas t remains active as long as wait states are inserted via the rdyrc v pin. blas t becomes inactive after the final data transfer in a bus cycle . 0 = last data transfer 1 = not last data transfe r rdyrc v i s(l ) read y /recove r indicates that data on ad lines can be sampled or removed. if rdyrc v is not asserted during a t d cycle, the t d cycle is extended to the next cycle by inserting a wait state ( t w ) . 0 = sample data 1 = don?t sample dat a the rdyrc v pin has another function during the recovery ( t r ) state. the processor continues to insert additional recovery states until it samples the pin high. this function gives slow external devices more time to float their buffers before the processor begins to drive address again . 0 = insert wait states 1 = recovery complet e loc k / onc e i/o s(l) r(h) h(z) p(1 ) bus loc k indicates that an atomic read-modify-write operation is in progress. the loc k output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. the processor does not grant holda while it is asserting loc k . this prevents external agents from accessing memory involved in semaphore operations . 0 = atomic read-modify-write in progress 1 = atomic read-modify-write not in progres s once mode: the processor samples the onc e input during reset. if it is asserted low at the end of reset, the processor enters once mode. in once mode, the processor stops all clocks and floats all output pins. the pin has a weak internal pullup which is active during reset to ensure normal operation when the pin is left unconnected . 0 = once mode enabled 1 = once mode not enable d table 3. pin description ? external bus signal s (sheet 3 of 4 ) nam e typ e descriptio n
1 0 preliminar y 80960j d a hol d i s(l ) hol d : a request from an external bus master to acquire the bus. when the processor receives hold and grants bus control to another master, it asserts holda, floats the address/data and control lines and enters the t h state. when hold is deasserted, the processor deasserts holda and enters either the t i or t a state, resuming control of the address/data and control lines . 0 = no hold request 1 = hold reques t hold a o r(q) h(1) p(q ) hold acknowledg e indicates to an external bus master that the processor has relinquished control of the bus. the processor can grant hold requests and enter the t h state during reset and while halted as well as during regular operation . 0 = hold not acknowledged 1 = hold acknowledge d bsta t o r(0) h(q) p(0 ) bus stat u s indicates that the processor may soon stall unless it has sufficient access to the bus; see i96 0 ? jx microprocessor user?s guide (272483 ) . arbitration logic can examine this signal to determine when an external bus master should acquire/relinquish the bus . 0 = no potential stall 1 = potential stal l table 4. pin description ? processor control signals, test signals and power (sheet 1 of 2 ) nam e typ e descriptio n clki n i cloc k input provides the processor?s fundamental time base; both the processor core and the external bus run at the clkin rate. all input and output timings are specified relative to a rising clkin edge . rese t i a(l ) rese t initializes the processor and clears its internal logic. during reset, the processor places the address/data bus and control output pins in their idle (inactive) states . during reset, the input pins are ignored with the exception of loc k / onc e , stest and hold . the rese t pin has an internal synchronizer. to ensure predictable processor initia l - ization during power up, rese t must be asserted a minimum of 10,000 clkin cycles with v c c and clkin stable. on a warm reset, rese t should be asserted for a minimum of 15 cycles . stes t i s(l ) self tes t enables or disables the processor?s internal self-test feature at initia l - ization. stest is examined at the end of reset. when stest is asserted, the processor performs its internal self-test and the external bus confidence test. when stest is deasserted, the processor performs only the external bus confidence test . 0 = self test disabled 1 = self test enable d table 3. pin description ? external bus signal s (sheet 4 of 4 ) nam e typ e descriptio n
preliminar y 1 1 a 80960j d fai l o r(0) h(q) p(1 ) fai l indicates a failure of the processor?s built-in self-test performed during initia l - ization. fai l is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests : ? when self-test passes, the processor deasserts fai l and begins operation from user code. ? when self-test fails, the processor asserts fai l and then stops executing . 0 = self test failed 1 = self test passe d tc k i test cloc k is a cpu input which provides the clocking function for iee e 1149.1 boundary scan testing (jtag). state information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge . td i i s(l ) test data inpu t is the serial input pin for jtag. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port . td o o r(q) hq) p(q ) test data outpu t is the serial output pin for jtag. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. tdo does not float during once mode . trs t i a(l ) test rese t asynchronously resets the test access port (tap) controller function of iee e 1149.1 boundary scan testing (jtag). when using the boundary scan feature, connect a pulldown resistor between this pin and v s s . if tap is not used, this pin must be connected to v s s ; however, no resistor is required. see section 4.3, connection recommendations (pg. 24 ) . tm s i s(l ) test mode select is sampled at the rising edge of tck to select the operation of the test logic for ieee 1149.1 boundary scan testing . v c c ? powe r pins intended for external connection to a v c c board plane . v ccpl l ? pll powe r is a separate v c c supply pin for the phase lock loop clock generator. it is intended for external connection to the v c c board plane. in noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships . v s s ? groun d pins intended for external connection to a v s s board plane . n c ? no connec t pins. do not make any system connections to these pins . table 4. pin description ? processor control signals, test signals and power (sheet 2 of 2 ) nam e typ e descriptio n
1 2 preliminar y 80960j d a table 5. pin description ? interrupt unit signals nam e typ e descriptio n xint7: 0 i a(e/l ) external interrup t pins are used to request interrupt service. the xint7: 0 pins can be configured in three modes : dedicated mod e : each pin is assigned a dedicated interrupt level. dedicated inputs can be programmed to be level (low) or edge (falling) sensitive . expanded mod e : all eight pins act as a vectored interrupt source. the interrupt pins are level sensitive in this mode . mixed mod e : the xint7: 5 pins act as dedicated sources and th e xint4: 0 pins act as the five most significant bits of a vectored source. the least significant bits of the vectored source are set to 01 0 2 internally . unused external interrupt pins should be connected to v c c . nm i i a(e ) non-maskable interrup t causes a non-maskable interrupt event to occur. nm i is the highest priority interrupt source and is falling edge-triggered. i f nm i is unused, it should be connected to v c c .
preliminar y 1 3 a 80960j d 3.1.2 80960j x 132-lead pga pinou t figure 3. 132-lead pin grid array bottom view - pins facing u p ad6 ad11 ad13 v cc v cc v cc v cc v cc v cc v cc ad18 ad19 ad22 ad25 ad3 ad7 ad10 v ss v ss v ss v ss v ss v ss v ss ad20 ad24 ad26 ad27 ad0 ad4 ad8 ad9 ad12 ad14 ad15 ad16 ad17 ad21 ad23 ad29 ad30 nc ad28 be3 be2 ad31 v ss v cc be1 v ss v cc be0 v ss v cc ale v cc bstat v ss v cc v ss v cc dt / r v ss v cc v cc ad1 v cc v ss v cc v ss nc clkin v ss v ccpll v cc v ss nc v cc rdyrcv v cc reset v cc v ss ad5 ad2 v ss tdi xint0 nc a2 width/ ads a3 xint1 tms xint2 nc stest trst hold nc fail nc blast lock/ holda tck xint3 xint5 xint7 nmi v cc v cc v cc v cc nc nc ale xint6 v ss v ss v ss v ss nc tdo width/ d / c w / r xint4 p n m l k j h g f e d c b a p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v ss den v ss hltd1 hltd0 once
1 4 preliminar y 80960j d a figure 4. 132-lead pin grid array top view - pins facing dow n tms nc nc v cc v cc v cc v cc clkin v cc v cc v cc ad0 ad3 ad6 xint2 tck stest v ss v ss v ss v ss v ss v ss v ss ad1 ad4 ad7 ad11 xint5 xint3 trst tdi reset rdyrcv nc v ccpll nc ad2 ad5 ad10 ad13 ad8 ad9 v ss v cc ad12 v ss v cc ad14 v ss v cc ad15 v ss v cc v cc ad17 v cc ad21 v ss v cc ad23 ad20 ad18 xint7 xint4 nmi xint6 v cc v ss hold v cc v ss nc v cc v ss nc v cc v ss fail nc a2 nc tdo xint0 xint1 nc a3 dt / r width/ ad31 ad27 ad25 ad28 den ads w / r ale width/ blast bstat ale be1 be0 nc ad19 ad24 d / c holda lock/ v cc v cc v cc v cc v cc v cc v cc be2 ad30 v ss v ss v ss v ss v ss v ss be3 ad29 ad26 ad22 p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ad16 v ss v ss hltd0 v ss hltd1 once i m ? 19xx a8 0 960 j d xxxxxxx x a 2
preliminar y 1 5 a 80960j d table 6. 132-lead pga pinout ? in signal order signa l pi n signa l pi n signa l pi n signa l pi n a 2 c 5 ad3 1 k 3 td i d1 2 v s s b 9 a 3 c 4 ad s a 1 td o b 4 v s s d 2 ad 0 m1 4 al e g 3 tm s a1 4 v s s d1 3 ad 1 l1 3 al e a 3 trs t c1 2 v s s e 2 ad 2 k1 2 be 0 h 3 v c c a 6 v s s e1 3 ad 3 n1 4 be 1 j 3 v c c a 7 v s s f 2 ad 4 m1 3 be 2 l 1 v c c a 8 v s s f1 3 ad 5 l1 2 be 3 l 2 v c c a 9 v s s g 2 ad 6 p1 4 blas t c 3 v c c d 1 v s s g1 3 ad 7 n1 3 bsta t f 3 v c c d1 4 v s s h 2 ad 8 m1 2 clki n h1 4 v c c e 1 v s s h1 3 ad 9 m1 1 d / c b 2 v c c e1 4 v s s j 2 ad1 0 n1 2 de n e 3 v c c f 1 v s s j1 3 ad1 1 p1 3 dt / r d 3 v c c f1 4 v s s k 2 ad1 2 m1 0 fai l c 6 v c c g 1 v s s k1 3 ad1 3 p1 2 hol d c 9 v c c g1 4 v s s n 5 ad1 4 m 9 hold a c 2 v c c h 1 v s s n 6 ad1 5 m 8 loc k / onc e c 1 v c c j 1 v s s n 7 ad1 6 m 7 n c a 4 v c c j1 4 v s s n 8 ad1 7 m 6 n c a 5 v c c k 1 v s s n 9 ad1 8 p 4 n c b 5 v c c k1 4 v s s n1 0 ad1 9 p 3 n c b1 4 v c c l1 4 v s s n1 1 ad2 0 n 4 n c c 7 v c c p 5 w / r b 1 ad2 1 m 5 n c c 8 v c c p 6 width/hltd 0 b 3 ad2 2 p 2 n c c1 4 v c c p 7 width/hltd 1 a 2 ad2 3 m 4 n c g1 2 v c c p 8 xint 0 c1 1 ad2 4 n 3 n c j1 2 v c c p 9 xint 1 c1 0 ad2 5 p 1 n c m 3 v c c p1 0 xint 2 a1 3 ad2 6 n 2 nm i a1 0 v c c p1 1 xint 3 b1 2 ad2 7 n 1 rdyrc v f1 2 v ccpl l h1 2 xint 4 b1 1 ad2 8 l 3 rese t e1 2 v s s b 6 xint 5 a1 2 ad2 9 m 2 stes t c1 3 v s s b 7 xint 6 b1 0 ad3 0 m 1 tc k b1 3 v s s b 8 xint 7 a1 1 note : do not connect any external logic to pins marked nc (no connect pins) .
1 6 preliminar y 80960j d a table 7. 132-lead pga pinout ? in pin order pi n signa l pi n signa l pi n signa l pi n signa l a 1 ad s c 6 fai l h 1 v c c m1 0 ad1 2 a 2 width/hltd 1 c 7 n c h 2 v s s m1 1 ad 9 a 3 al e c 8 n c h 3 be 0 m1 2 ad 8 a 4 n c c 9 hol d h1 2 v ccpl l m1 3 ad 4 a 5 n c c1 0 xint 1 h1 3 v s s m1 4 ad 0 a 6 v c c c1 1 xint 0 h1 4 clki n n 1 ad2 7 a 7 v c c c1 2 trs t j 1 v c c n 2 ad2 6 a 8 v c c c1 3 stes t j 2 v s s n 3 ad2 4 a 9 v c c c1 4 n c j 3 be 1 n 4 ad2 0 a1 0 nm i d 1 v c c j1 2 n c n 5 v s s a1 1 xint 7 d 2 v s s j1 3 v s s n 6 v s s a1 2 xint 5 d 3 dt / r j1 4 v c c n 7 v s s a1 3 xint 2 d1 2 td i k 1 v c c n 8 v s s a1 4 tm s d1 3 v s s k 2 v s s n 9 v s s b 1 w / r d1 4 v c c k 3 ad3 1 n1 0 v s s b 2 d / c e 1 v c c k1 2 ad 2 n1 1 v s s b 3 width/hltd 0 e 2 v s s k1 3 v s s n1 2 ad1 0 b 4 td o e 3 de n k1 4 v c c n1 3 ad 7 b 5 n c e1 2 rese t l 1 be 2 n1 4 ad 3 b 6 v s s e1 3 v s s l 2 be 3 p 1 ad2 5 b 7 v s s e1 4 v c c l 3 ad2 8 p 2 ad2 2 b 8 v s s f 1 v c c l1 2 ad 5 p 3 ad1 9 b 9 v s s f 2 v s s l1 3 ad 1 p 4 ad1 8 b1 0 xint 6 f 3 bsta t l1 4 v c c p 5 v c c b1 1 xint 4 f1 2 rdyrc v m 1 ad3 0 p 6 v c c b1 2 xint 3 f1 3 v s s m 2 ad2 9 p 7 v c c b1 3 tc k f1 4 v c c m 3 n c p 8 v c c b1 4 n c g 1 v c c m 4 ad2 3 p 9 v c c c 1 loc k / onc e g 2 v s s m 5 ad2 1 p1 0 v c c c 2 hold a g 3 al e m 6 ad1 7 p1 1 v c c c 3 blas t g1 2 n c m 7 ad1 6 p1 2 ad1 3 c 4 a 3 g1 3 v s s m 8 ad1 5 p1 3 ad1 1 c 5 a 2 g1 4 v c c m 9 ad1 4 p1 4 ad 6 note : do not connect any external logic to pins marked nc (no connect pins) .
preliminar y 1 7 a 80960j d 3.1.3 80960j x pqfp pinou t figure 5. 132-lead pqfp - top vie w a d 8 a d 7 a d 6 a d 5 a d 4 v c c ( i / o ) v s s ( i / o ) a d 3 a d 2 a d 1 a d 0 v c c ( i / o ) v c c ( c o r e ) v s s ( c o r e ) v c c ( c o r e ) v s s ( c o r e ) v c c p l l v c c ( c l k ) n c n c r d y r c v v s s ( c o r e ) r e s e t n c s t e s t v c c ( i / o ) t d i v s s ( i / o ) a d 2 7 v c c ( i / o ) v s s ( i / o ) a d 2 8 a d 2 9 a d 3 0 a d 3 1 v c c ( c o r e ) v s s ( c o r e ) v c c ( i / o ) v s s ( i / o ) b e 3 b e 2 b e 1 b e 0 b s t a t l o c k / o n c e v c c ( i / o ) v s s ( i / o ) v c c ( c o r e ) v s s ( c o r e ) a l e h o l d a d e n d t / r v c c ( i / o ) v s s ( i / o ) v c c ( c o r e ) v s s ( c o r e ) w / r a d s d / c b l a s t 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 trst tck tms hold xint0 xint1 xint2 xint3 v c c (i/o) v s s (i/o) xint4 xint5 xint6 xint7 nmi v c c (core) v s s (core) nc nc nc nc nc fail ale tdo v c c (i/o) v s s (i/o) width/hltd1 v c c (core) v s s (core) width/hltd0 a2 a3 ad9 v c c (i/o) ad10 v s s (i/o) v c c (i/o) ad11 v s s (i/o) v c c (core) v s s (core) ad12 ad13 ad14 ad15 v c c (i/o) v s s (i/o) ad16 ad17 ad18 ad19 nc v c c (i/o) ad22 ad25 ad21 ad20 ad24 ad26 ad23 v s s (i/o) v c c (core) v c c (i/o) v s s (core) v s s (i/o) v s s ( i / o ) c l k i n v s s ( c l k ) n c v c c ( c o r e ) i xxxxxxx x a2 m ? 19xx i96 0 ? a ng8 0 960 j x
1 8 preliminar y 80960j d a table 8. 132-lead pqfp pinout ? in signal order signa l pi n signa l pi n signa l pi n signa l pi n ad3 1 6 0 al e 2 4 v c c (core ) 4 7 v s s (i/o ) 1 0 ad3 0 6 1 ad s 3 6 v c c (core ) 5 9 v s s (i/o ) 2 7 ad2 9 6 2 a 3 3 3 v c c (core ) 7 4 v s s (i/o ) 4 0 ad2 8 6 3 a 2 3 2 v c c (core ) 9 2 v s s (i/o ) 4 8 ad2 7 6 6 be 3 5 5 v c c (core ) 11 3 v s s (i/o ) 5 6 ad2 6 6 8 be 2 5 4 v c c (core ) 11 5 v s s (i/o ) 6 4 ad2 5 6 9 be 1 5 3 v cc (core ) 12 3 v s s (i/o ) 7 1 ad2 4 7 0 be 0 5 2 v c c (i/o ) 9 v s s (i/o ) 7 9 ad2 3 7 5 width/hltd 1 2 8 v c c (i/o ) 2 6 v s s (i/o ) 8 5 ad2 2 7 6 width/hltd 0 3 1 v cc (i/o ) 4 1 v s s (i/o ) 9 3 ad2 1 7 7 d / c 3 5 v c c (i/o ) 4 9 v s s (i/o ) 9 7 ad2 0 7 8 w / r 3 7 v c c (i/o ) 5 7 v s s (i/o ) 10 6 ad1 9 8 1 dt / r 4 2 v c c (i/o ) 6 5 v s s (i/o ) 11 2 ad1 8 8 2 de n 4 3 v c c (i/o ) 7 2 v s s (i/o ) 13 1 ad1 7 8 3 blas t 3 4 v c c (i/o ) 8 0 n c 1 8 ad1 6 8 4 rdyrc v 13 2 v c c (i/o ) 8 6 n c 1 9 ad1 5 8 7 loc k / onc e 5 0 v c c (i/o ) 9 4 n c 2 0 ad1 4 8 8 hol d 4 v c c (i/o ) 9 8 n c 2 1 ad1 3 8 9 hold a 4 4 v c c (i/o ) 10 5 n c 2 2 ad1 2 9 0 bsta t 5 1 v c c (i/o ) 11 1 n c 6 7 ad1 1 9 5 clki n 11 7 v c c (i/o ) 12 9 n c 12 1 ad1 0 9 6 rese t 12 5 v ccpl l 11 9 n c 12 2 ad 9 9 9 stes t 12 8 v s s (clk ) 11 8 n c 12 6 ad 8 10 0 fai l 2 3 v s s (core ) 1 7 n c 12 7 ad 7 10 1 tc k 2 v s s (core ) 3 0 xint 7 1 4 ad 6 10 2 td i 13 0 v s s (core ) 3 8 xint 6 1 3 ad 5 10 3 td o 2 5 v s s (core ) 4 6 xint 5 1 2 ad 4 10 4 trs t 1 v s s (core ) 5 8 xint 4 1 1 ad 3 10 7 tm s 3 v s s (core ) 7 3 xint 3 8 ad 2 10 8 v c c (clk ) 12 0 v s s (core ) 9 1 xint 2 7 ad 1 10 9 v c c (core ) 1 6 v s s (core ) 11 4 xint 1 6 ad 0 11 0 v c c (core ) 2 9 v s s (core ) 11 6 xint 0 5 al e 4 5 v c c (core ) 3 9 v ss (core ) 12 4 nm i 1 5 note : do not connect any external logic to pins marked nc (no connect pins) .
preliminar y 1 9 a 80960j d table 9. 132-lead pqfp pinout ? in pin orde r pi n signa l pi n signa l pi n signa l pi n signa l 1 trs t 3 4 blas t 6 7 n c 10 0 ad 8 2 tc k 3 5 d / c 6 8 ad2 6 10 1 ad 7 3 tm s 3 6 ad s 6 9 ad2 5 10 2 ad 6 4 hol d 3 7 w / r 7 0 ad2 4 10 3 ad 5 5 xint 0 3 8 v s s (core ) 7 1 v ss (i/o ) 10 4 ad 4 6 xint 1 3 9 v cc (core ) 7 2 v cc (i/o ) 10 5 v cc (i/o ) 7 xint 2 4 0 v ss (i/o ) 7 3 v ss (core ) 10 6 v ss (i/o ) 8 xint 3 4 1 v cc (i/o ) 7 4 v cc (core ) 10 7 ad 3 9 v cc (i/o ) 4 2 dt / r 7 5 ad2 3 10 8 ad 2 1 0 v ss (i/o ) 4 3 de n 7 6 ad2 2 10 9 ad 1 1 1 xint 4 4 4 hold a 7 7 ad2 1 11 0 ad 0 1 2 xint 5 4 5 al e 7 8 ad2 0 11 1 v cc (i/o ) 1 3 xint 6 4 6 v ss (core ) 7 9 v ss (i/o ) 11 2 v ss (i/o ) 1 4 xint 7 4 7 v cc (core ) 8 0 v cc (i/o ) 11 3 v cc (core ) 1 5 nm i 4 8 v ss (i/o ) 8 1 ad1 9 11 4 v ss (core ) 1 6 v cc (core ) 4 9 v cc (i/o ) 8 2 ad1 8 11 5 v cc (core ) 1 7 v ss (core ) 5 0 loc k / onc e 8 3 ad1 7 11 6 v ss (core ) 1 8 n c 5 1 bsta t 8 4 ad1 6 11 7 clki n 1 9 n c 5 2 be 0 8 5 v ss (i/o ) 11 8 v ss (clk ) 2 0 n c 5 3 be 1 8 6 v cc (i/o ) 11 9 v ccpl l 2 1 n c 5 4 be 2 8 7 ad1 5 12 0 v cc (clk ) 2 2 n c 5 5 be 3 8 8 ad1 4 12 1 n c 2 3 fai l 5 6 v ss (i/o ) 8 9 ad1 3 12 2 n c 2 4 al e 5 7 v cc (i/o ) 9 0 ad1 2 12 3 v cc (core ) 2 5 td o 5 8 v ss (core ) 9 1 v ss (core ) 12 4 v s s (core ) 2 6 v cc (i/o ) 5 9 v cc (core ) 9 2 v cc (core ) 12 5 rese t 2 7 v ss (i/o ) 6 0 ad3 1 9 3 v ss (i/o ) 12 6 n c 2 8 width/hltd 1 6 1 ad3 0 9 4 v cc (i/o ) 12 7 n c 2 9 v cc (core ) 6 2 ad2 9 9 5 ad1 1 12 8 stes t 3 0 v ss (core ) 6 3 ad2 8 9 6 ad1 0 12 9 v cc (i/o ) 3 1 width/hltd 0 6 4 v ss (i/o ) 9 7 v ss (i/o ) 13 0 td i 3 2 a 2 6 5 v cc (i/o ) 9 8 v cc (i/o ) 13 1 v ss (i/o ) 3 3 a 3 6 6 ad2 7 9 9 ad 9 13 2 rdyrc v note : do not connect any external logic to pins marked nc (no connect pins) .
80960j d a 2 0 preliminar y 3.2 package thermal specification s the 80960j d is specified for operation when t c (case temperature) is within the range o f 0c to 85 c for th e (pga) 80960JD-50, o r 0c to 100 c for the (pqfp and pga) 80960jd-40 and 80960jd-3 3 . case temperature may be measured in any environment to determine whether the 80960j d is within specified operating range. the case tempe r - ature should be measured at the center of the top surface, opposite the pins . q c a is the thermal resistance from case to ambient. use the following equation to calculate t a , the maximum ambient temperature to conform to a particular case temperature : t a = t c - p ( q c a ) junction temperature ( t j ) is commonly used in reliability calculations. t j can be calculated from q jc (thermal resistance from junction to case) using the following equation : t j = t c + p ( q j c ) similarly, if t a is known, the corresponding case temperature ( t c ) can be calculated as follows : t c = t a + p ( q c a ) compute p by multiplying i c c from table 1 4 and v c c . values for q j c and q c a are given in table 1 0 for the pga package and table 1 1 for the pqfp package. for high speed operation, the processor?s q j a may be significantly reduced by adding a heatsink and/or by increasing airflow . figure 6 shows the maximum ambient temperature ( t a ) permitted without exceeding t c for the 80960j d -50 in a pga package. figure 7 illustrates this for the 80960jd-40 in pga and pqfp packages. the curves are based on minimum i cc (hot) and maximum v c c of +5.2 5 v, with a t cas e of +85c for the 80960JD-50, or a t cas e of +100c for the 80960jd-40 . table 10. 132-lead pga package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 (0 ) 20 0 (1.01 ) 40 0 (2.03 ) 60 0 (3.04 ) 80 0 (4.06 ) 100 0 (5.08 ) q j c (junction-to-case ) 3 3 3 3 3 3 q c a (case-to-ambient) (no heatsink ) 1 8 1 5 1 2 1 1 1 1 1 1 q c a (case-to-ambient) (omnidirectional heatsink ) 1 5 1 2 9 8 8 8 q c a (case-to-ambient) (unidirectional heatsink ) 1 4 1 1 8 7 7 7 note s : 1. this table applies to a pga device plugged into a socket or soldered directly into a board . 2. q j a = q j c + q c a 3. q j-ca p = 4c/w (approx. ) 4. q j-pi n = 4c/w (inner pins) (approx. ) 5. q j-pi n = 8c/w (outer pins) (approx. ) q jc q ja q j-cap q ca q j-pin
preliminar y 2 1 a 80960j d figure 6. 50 mhz maximum allowable ambient temperature table 11. 132-lead pqfp package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 (0 ) 5 0 (0.25 ) 10 0 (0.50 ) 20 0 (1.01 ) 40 0 (2.03 ) 60 0 (3.04 ) 80 0 (4.06 ) q j c (junction-to-case ) 6 7 7 7 7 7 7 q c a (case-to-ambient -no heatsink ) 2 3 2 0 1 8 1 4 1 0 9 8 notes : 1. this table applies to a pqfp device soldered directly into board . 2. q j a = q j c + q c a 3. q j l = 18c/w (approx. ) 4. q j b = 18c/w (approx. ) q jb q ja q jc q jl q ca airflow (ft/min) t e m p e r a t u r e ( o c ) 65 60 55 50 45 40 35 30 0 100 200 300 400 500 600 700 800 pga with no heatsink pga with omnidirectional heatsink pga with unidirectional heatsink
2 2 preliminar y 80960j d a figure 7. 40 mhz maximum allowable ambient temperature airflow (ft/min) t e m p e r a t u r e ( o c ) 85 80 75 70 65 60 55 50 0 50 100 200 300 400 500 600 700 pga with no heatsink pga with omnidirectional heatsink pga with unidirectional heatsink 45 40 pqfp 800 3.3 thermal management accessorie s the following is a list of suggested sources for 80960j d thermal solutions. this is neither an endorsement or a warranty of the performance of any of the listed products and/or companies . heatsink s 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75234-8993 (214) 243-4321 fax: (214) 241-465 6 2. wakefield engineering 60 audubon road wakefield, ma 01880 (617) 245-590 0 3. aavid thermal technologies, inc. one kool path laconia, nh 03247-0400 (603) 528-340 0
a 80960j d preliminar y 2 3 4.0 e lectrical specification s 4.1 absolute maximum rating s paramete r maximum ratin g storage temperature .............................. ?6 5 c to +15 0 c case temperature under bias ............... ?6 5 c to +11 0 c supply voltage wrt. v s s .............................. ?0.5v to + 4.6 v voltage on other pins wrt. v ss ........... ?0.5v to v c c + 0.5 v notice : this data sheet contains preliminary information on new products in production. the specifications are subject to change without notice . warning : stressing the device beyond the ?abs o - lute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not reco m - mended and extended exposure beyond the ?ope r - ating conditions? may affect device reliability . 4.2 operating condition s table 12. 80960j d operating conditions symbo l paramete r mi n ma x unit s note s v c c supply voltag e 80960j d -50 80960j d -40 80960j d -3 3 4.75 4.75 4.7 5 5.25 5.25 5.2 5 v f clki n input clock frequenc y 80960JD-50 80960j d -40 80960j d -3 3 8 8 8 25 20 16.6 7 mh z t c operating case temperatur e a 80960j d -50 (132 pga) a 80960j d -40 (132 pga) a 80960j d -33 (132 pga) ng80960jd-40 (132 pqfp) n g 80960j d -33 (132 pqfp ) 0 0 0 0 0 85 100 100 100 10 0 c
80960j d a 2 4 preliminar y 4.3 connection recommendation s for clean on-chip power distribution, v c c and v ss pins separately feed the device?s functional units. power and ground connections must be made to all 80960j d power and ground pins. on the circuit board, every v c c pin should connect to a power plane and every v s s pin should connect to a ground plane. place liberal decoupling capacitance near the 80960j d , since the processor can cause transient power surges. pay special attention to the test reset ( trs t ) pin. it is essential that the jtag boundary scan test access port (tap) controller initializes to a known state whether it will be used or not. if the jtag boundary scan function will be used, connect a pulldown resistor between t he trs t pin and v s s . if the jtag boundary scan function will not be used (even for board-level testing), connect the trs t pin to v s s . also, do not connect the tdi, tdo, and tck pins if the tap controller will not be used . pins identified as nc must not be connected in the syste m . 4.4 dc specification s table 13. 80960j d dc characteristics symbo l paramete r mi n ty p ma x unit s note s v i l input low voltage -0. 3 0. 8 v v i h input high voltag e 2. 0 v c c + 0. 3 v v o l output low voltag e 0.4 5 v i o l = 5 m a v o h output high voltag e 2. 4 v c c - 0.5 v i o h = -1 m a i o h = -200 m a v ol p output ground bounc e < 0. 8 v (1,2 ) c i n input capacitance pga pqf p 12 1 0 p f f clki n = f mi n (2 ) c ou t i/o or output capacitance pga pqf p 12 1 0 p f f clki n = f mi n (2 ) c cl k clkin capacitance pga pqf p 12 1 0 p f f clki n = f mi n (2 ) notes : 1. typical is measured with v c c = 5.0v and temperature = 2 5 c . 2. not tested .
preliminar y 2 5 a 80960j d table 14. 80960j d i c c characteristics symbo l paramete r ty p ma x unit s note s i li 1 input leakage current for each pin except tck, tdi, trs t and tm s 1 m a 0 v i n v c c i li 2 input leakage current for tck, tdi , trs t and tm s -14 0 -25 0 m a v i n = 0.45v (1 ) i l o output leakage curren t 1 m a 0. 4 v ou t v c c i cc active (power supply ) 80960jd-5 0 80960jd-4 0 80960jd-3 3 64 0 53 0 45 0 m a (2,3 ) (2,3 ) (2,3 ) i cc active (thermal ) 80960jd-5 0 80960jd-4 0 80960jd-3 3 52 5 43 0 36 5 m a (2,4 ) (2,4 ) (2,4 ) i cc test (power modes ) reset mod e 80960jd-5 0 80960jd-4 0 80960jd-3 3 halt mod e 80960jd-5 0 80960jd-4 0 80960jd-3 3 once mod e 51 0 43 0 37 0 4 8 4 1 3 6 1 0 m a (5 ) (5 ) (5 ) (5 ) (5 ) (5 ) (5 ) notes : 1. these pins have internal pullup devices. typical leakage current is not tested . 2. measured with device operating and outputs loaded to the test condition in figure 8, ac test load (pg. 33 ) . 3. i c c active (power supply) value is provided for selecting your system?s power supply. it is measured using one of the worst case instruction mixes with v c c = 5.25v. this parameter is characterized but not tested . 4. i c c active (thermal) value is provided for your system?s thermal management. typical i c c is measured with v cc = 5.0v and temperature = 2 5 c. this parameter is characterized but not tested . 5. i c c test (power modes) refers to the i c c values that are tested when the 80960jd is in reset mode, halt mode or once mode with v c c = 5.25v .
2 6 preliminar y 80960j d a 4.5 ac specification s th e 80960j d ac timings are based upon device characterization . table 15. 80960j d ac characteristics (50 mhz ) (sheet 1 of 2 ) symbo l paramete r mi n ma x unit s note s input clock timing s t f clkin frequenc y 8 2 5 mh z t c clkin perio d 4 0 12 5 n s t c s clkin period stabilit y 25 0 p s (1, 2 ) t c h clkin high tim e 1 6 n s measured at 1.5 v (1 ) t c l clkin low tim e 1 6 n s measured at 1.5 v (1 ) t c r clkin rise tim e 2 5 n s 0.8 v to 2.0 v (1 ) t c f clkin fall tim e 5 n s 2.0 v to 0.8 v (1 ) synchronous output timing s t ov 1 output valid delay, except ale / al e inactive and dt / r 3. 5 1 7 n s (3 ) t ov 2 output valid delay, dt / r 0.5 t c + 3. 5 0.5 t c + 1 7 n s t o f output float dela y 3. 5 1 5 n s (4 ) synchronous input timing s t is 1 input setup to clkin ? ad31:0, nm i , xint7: 0 8 n s (5 ) t ih 1 input hold from clkin ? ad31:0, nm i , xint7: 0 2 n s (5 ) t is 2 input setup to clkin ? rdyrc v and hol d 9 n s (6 ) t ih 2 input hold from clkin ? rdyrc v and hol d 1 n s (6 ) t is 3 input setup to clkin ? rese t 8 n s (7 ) t ih 3 input hold from clkin ? rese t 2 n s (7 ) t is 4 input setup to rese t ? onc e , stes t 8 n s (8 ) t ih 4 input hold from rese t ? onc e , stes t 2 n s (8 ) note: see tabl e 16 on pag e 2 8 for note definitions for this table .
preliminar y 2 7 a 80960j d relative output timing s t lx l ale / al e widt h 0.5 t c - 7. 5 n s (9 ) t lx a address hold from ale / al e inactiv e equal loading (9 ) t dx d dt / r valid to de n activ e equal loading (9 ) boundary scan test signal timing s t bs f tck frequenc y 0.5 t f mh z t bsc h tck high tim e 1 5 n s measured at 1.5 v (1 ) t bsc l tck low tim e 1 5 n s measured at 1.5 v (1 ) t bsc r tck rise tim e 5 n s 0.8 v to 2.0 v (1 ) t bsc f tck fall tim e 5 n s 2.0 v to 0.8 v (1 ) t bsis 1 input setup to tck ? tdi, tm s 4 n s t bsih 1 input hold from tck ? tdi, tm s 6 n s t bsov 1 tdo valid dela y 3 3 0 n s (1,10 ) t bsof 1 tdo float dela y 3 3 0 n s (1,10 ) t bsov 2 all outputs (non-test) valid dela y 3 3 0 n s (1,10 ) t bsof 2 all outputs (non-test) float dela y 3 3 0 n s (1,10 ) t bsis 2 input setup to tck ? all inputs (non-test) 4 n s t bsih 2 input hold from tck ? all inputs (non-test ) 6 n s table 15. 80960j d ac characteristics (50 mhz ) (sheet 2 of 2 ) symbo l paramete r mi n ma x unit s note s note: see tabl e 16 on pag e 2 8 for note definitions for this table .
2 8 preliminar y 80960j d a table 16. note definitions for table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) notes : 1. not tested. 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the clkin frequency. 3. inactive ale / al e refers to the falling edge of ale and the rising edge of al e . for inactive ale / ale timings, refer to relative output timings in this table . 4. a float condition occurs when the output current becomes less than i l o . float delay is not tested, but is designed to be no longer than the valid delay. 5. ad31:0 are synchronous inputs. setup and hold times must be met for proper processor operation. nmi and xint7: 0 may be synchronous or asynchronous. meeting setup and hold time guarantees reco g - nition at a particular clock edge. for asynchronous operation, nm i and xint7: 0 must be asserted for a minimum of two clkin periods to guarantee recognition . 6. rdyrc v and hold are synchronous inputs. setup and hold times must be met for proper processor operation . 7. rese t may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge . 8. onc e and stes t must be stable at the rising edge of rese t for proper operation . 9. guaranteed by design. may not be 100% tested . 10. relative to falling edge of tck . table 17. 80960j d ac characteristics (40 mhz ) (sheet 1 of 3 ) symbo l paramete r mi n ma x unit s note s input clock timing s t f clkin frequenc y 8 2 0 mh z t c clkin perio d 5 0 12 5 n s t c s clkin period stabilit y 25 0 p s (1, 2 ) t c h clkin high tim e 2 0 n s measured at 1.5 v (1 ) t c l clkin low tim e 2 0 n s measured at 1.5 v (1 ) t c r clkin rise tim e 7 n s 0.8 v to 2.0 v (1 ) t c f clkin fall tim e 7 n s 2.0 v to 0.8 v (1 ) synchronous output timing s t ov 1 output valid delay, except ale / al e inactive and dt / r 3. 5 1 8 n s (3 )
preliminar y 2 9 a 80960j d t ov 2 output valid delay, dt / r 0.5 t c + 3. 5 0.5 t c + 1 8 n s t o f output float dela y 3. 5 1 6 n s (4 ) synchronous input timing s t is 1 input setup to clkin ? ad31:0, nm i , xint7: 0 8 n s (5 ) t ih 1 input hold from clkin ? ad31:0, nm i , xint7: 0 2 n s (5 ) t is 2 input setup to clkin ? rdyrc v and hol d 9 n s (6 ) t ih 2 input hold from clkin ? rdyrc v and hol d 1 n s (6 ) t is 3 input setup to clkin ? rese t 8 n s (7 ) t ih 3 input hold from clkin ? rese t 2 n s (7 ) t is 4 input setup to rese t ? onc e , stes t 8 n s (8 ) t ih 4 input hold from rese t ? onc e , stes t 2 n s (8 ) relative output timing s t lx l ale / al e widt h 0.5 t c - 7. 5 n s (9 ) t lx a address hold from ale / al e inactiv e equal loading (9 ) t dx d dt / r valid to de n activ e equal loading (9 ) boundary scan test signal timing s t bs f tck frequenc y 0.5 t f mh z t bsc h tck high tim e 1 5 n s measured at 1.5 v (1 ) t bsc l tck low tim e 1 5 n s measured at 1.5 v (1 ) t bsc r tck rise tim e 5 n s 0.8 v to 2.0 v (1 ) t bsc f tck fall tim e 5 n s 2.0 v to 0.8 v (1 ) t bsis 1 input setup to tck ? tdi, tm s 4 n s t bsih 1 input hold from tck ? tdi, tm s 6 n s t bsov 1 tdo valid dela y 3 3 0 n s (1, 10 ) t bsof 1 tdo float dela y 3 3 0 n s (1, 10 ) table 17. 80960j d ac characteristics (40 mhz ) (sheet 2 of 3 ) symbo l paramete r mi n ma x unit s note s
3 0 preliminar y 80960j d a t bsov 2 all outputs (non-test) valid dela y 3 3 0 n s (1, 10 ) t bsof 2 all outputs (non-test) float dela y 3 3 0 n s (1, 10 ) t bsis 2 input setup to tck ? all inputs (non- test) 4 n s t bsih 2 input hold from tck ? all inputs (non- test ) 6 n s notes : 1. not tested. 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the clkin frequency. 3. inactive ale / al e refers to the falling edge of ale and the rising edge of al e . for inactive ale / ale timings, refer to relative output timings in this table . 4. a float condition occurs when the output current becomes less than i l o . float delay is not tested, but is designed to be no longer than the valid delay. 5. ad31:0 are synchronous inputs. setup and hold times must be met for proper processor operation. nmi and xint7: 0 may be synchronous or asynchronous. meeting setup and hold time guarantees reco g - nition at a particular clock edge. for asynchronous operation, nm i and xint7: 0 must be asserted for a minimum of two clkin periods to guarantee recognition . 6. rdyrc v and hold are synchronous inputs. setup and hold times must be met for proper processor operation . 7. rese t may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge . 8. onc e and stes t must be stable at the rising edge of rese t for proper operation . 9. guaranteed by design. may not be 100% tested . 10. relative to falling edge of tck . table 17. 80960j d ac characteristics (40 mhz ) (sheet 3 of 3 ) symbo l paramete r mi n ma x unit s note s
preliminar y 3 1 a 80960j d table 18. 80960j d ac characteristics (33 mhz ) (sheet 1 of 2 ) symbo l paramete r mi n ma x unit s note s input clock timing s t f clkin frequenc y 8 16.6 7 mh z t c clkin perio d 6 0 12 5 n s t c s clkin period stabilit y 25 0 p s (1, 2 ) t c h clkin high tim e 2 4 n s measured at 1.5 v (1 ) t c l clkin low tim e 2 4 n s measured at 1.5 v (1 ) t c r clkin rise tim e 8 n s 0.8 v to 2.0 v (1 ) t c f clkin fall tim e 8 n s 2.0 v to 0.8 v (1 ) synchronous output timing s t ov 1 output valid delay, except ale / al e inactive and dt / r 3. 5 1 9 n s (3 ) t ov 2 output valid delay, dt / r 0.5 t c + 3. 5 0.5 t c + 1 9 n s t o f output float dela y 3. 5 1 8 n s (4 ) synchronous input timing s t is 1 input setup to clkin ? ad31:0, nm i , xint7: 0 8 n s (5 ) t ih 1 input hold from clkin ? ad31:0, nm i , xint7: 0 2 n s (5 ) t is 2 input setup to clkin ? rdyrc v and hol d 9 n s (6 ) t ih 2 input hold from clkin ? rdyrc v and hol d 1 n s (6 ) t is 3 input setup to clkin ? rese t 8 n s (7 ) t ih 3 input hold from clkin ? rese t 2 n s (7 ) t is 4 input setup to rese t ? onc e , stes t 8 n s (8 ) t ih 4 input hold from rese t ? onc e , stes t 2 n s (8 ) relative output timing s t lx l ale / al e widt h 0.5 t c - 8 n s (9 ) t lx a address hold from ale / al e ina c - tiv e equal loading (9 ) t dx d dt / r valid to de n activ e equal loading (9 )
3 2 preliminar y 80960j d a boundary scan test signal timing s t bs f tck frequenc y 0.5 t f mh z t bsc h tck high tim e 1 5 n s measured at 1.5 v (1 ) t bsc l tck low tim e 1 5 n s measured at 1.5 v (1 ) t bsc r tck rise tim e 5 n s 0.8 v to 2.0 v (1 ) t bsc f tck fall tim e 5 n s 2.0 v to 0.8 v (1 ) t bsis 1 input setup to tck ? tdi, tm s 4 n s t bsih 1 input hold from tck ? tdi, tm s 6 n s t bsov 1 tdo valid dela y 3 3 0 n s (1, 10 ) t bsof 1 tdo float dela y 3 3 0 n s (1, 10 ) t bsov 2 all outputs (non-test) valid dela y 3 3 0 n s (1, 10 ) t bsof 2 all outputs (non-test) float dela y 3 3 0 n s (1, 10 ) t bsis 2 input setup to tck ? all inputs (non-test) 4 n s t bsih 2 input hold from tck ? all inputs (non-test ) 6 n s notes : 1. not tested. 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the clkin frequency. 3. inactive ale / al e refers to the falling edge of ale and the rising edge of al e . for inactive ale / ale timings, refer to relative output timings in this table . 4. a float condition occurs when the output current becomes less than i l o . float delay is not tested, but is designed to be no longer than the valid delay. 5. ad31:0 are synchronous inputs. setup and hold times must be met for proper processor operation. nmi and xint7: 0 may be synchronous or asynchronous. meeting setup and hold time guarantees reco g - nition at a particular clock edge. for asynchronous operation, nm i and xint7: 0 must be asserted for a minimum of two clkin periods to guarantee recognition . 6. rdyrc v and hold are synchronous inputs. setup and hold times must be met for proper processor operation . 7. rese t may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge . 8. onc e and stes t must be stable at the rising edge of rese t for proper operation . 9. guaranteed by design. may not be 100% tested . 10. relative to falling edge of tck . table 18. 80960j d ac characteristics (33 mhz ) (sheet 2 of 2 ) symbo l paramete r mi n ma x unit s note s
preliminar y 3 3 a 80960j d 4.5.1 ac test conditions and derating curve s the ac specifications in section 4.5, ac specification s are tested with the 5 0 pf load indicated in figure 8 . figure 9 shows how timings vary with load capacitance; figure 1 0 shows how output rise and fall times vary with load capacitance . figure 8. ac test loa d figure 9. output delay or hold vs. load capacitanc e output pin c l = 50 pf for all signals c l 50 100 150 o u t p u t v a l i d d e l a y ( n s ) @ 1 . 5 v c l (pf) nom +4 nom +2 nom nom -2 ac derating curves nom +6 high-to-low transitions low-to-high transitions
3 4 preliminar y 80960j d a figure 10. rise and fall time deratin g 4.5.2 ac timing waveform s figure 11. clkin wavefor m 50 100 150 c l (pf) 10 8 6 4 2 t i m e ( n s ) 2.0v to 0.8v transitions 0.8v to 2.0v transitions 2.0v 1.5v 0.8v t cf t ch t cl t c t cr
preliminar y 3 5 a 80960j d figure 12. output delay waveform for t ov 1 figure 13. output float waveform for t o f clkin ad31:0, ale (active), al e (active), ad s , a3:2, be3:0, width/hltd1:0, d / c , w / r , de n , blas t , loc k , holda, bstat, fail 1.5v 1.5v 1.5v t ov1 1.5v 1.5v t of clkin ad31:0, ale, ale ad s , a3:2, be3:0, width/hltd1:0, d / c , w / r , dt / r , de n , blas t , lock
3 6 preliminar y 80960j d a figure 14. input setup and hold waveform for t is 1 and t ih 1 figure 15. input setup and hold waveform for t is 2 and t ih 2 clkin ad31:0 1.5v 1.5v 1.5v t is1 t ih1 1.5v nmi xint7:0 valid clkin valid hold, 1.5v 1.5v 1.5v 1.5v 1.5v t is2 t ih2 rdyrcv
preliminar y 3 7 a 80960j d figure 16. input setup and hold waveform for t is 3 and t ih 3 figure 17. input setup and hold waveform for t is 4 and t ih 4 clkin reset 1.5v 1.5v t ih3 t is3 reset valid once, t is4 t ih4 stest
3 8 preliminar y 80960j d a figure 18. relative timings waveform for t lx l and t lx a figure 19. dt / r and de n timings wavefor m clkin ale 1.5v 1.5v 1.5v ale 1.5v 1.5v ad31:0 valid t lxa t a t w / t d 1.5v valid 1.5v t lxl clkin dt / r 1.5v 1.5v 1.5v den valid t dxd t a t w / t d t ov1 t ov2
preliminar y 3 9 a 80960j d figure 20. tck wavefor m figure 21. input setup and hold waveforms for t bsis 1 and t bsih 1 2.0v 1.5v 0.8v t bsch t bscl t bscf t bscr tck tms 1.5v 1.5v 1.5v tdi 1.5v 1.5v valid t bsis1 t bsih1
4 0 preliminar y 80960j d a figure 22. output delay and output float waveform for t bsov 1 and t bsof 1 figure 23. output delay and output float waveform for t bsov 2 and t bsof 2 tck 1.5v 1.5v 1.5v t bsov1 tdo valid t bsof1 1.5v tck 1.5v 1.5v 1.5v t bsov2 non-test valid t bsof2 outputs 1.5v
preliminar y 4 1 a 80960j d figure 24. input setup and hold waveform for t bsis 2 and t bsih 2 tck non-test 1.5v 1.5v 1.5v 1.5v 1.5v valid t bsis2 t bsih2 inputs
4 2 preliminar y 80960j d a 5.0 bus functional waveform s figures 2 5 through 3 0 illustrate typical 80960j d bus transactions. figure 3 1 depicts the bus arbitration sequence. figure 3 2 illustrates the processor reset sequence from the time power is applied to the device. figure 3 3 illustrates the processor reset sequence when the processor is in operation. figure 3 4 illustrates the processor onc e sequence from the time power is applied to the device. figures 3 5 and 3 6 also show accesses on 32-bit buses. tables 1 9 through 2 2 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment . figure 25. non-burst read and write transactions without wait states, 32-bit bu s clkin ad31:0 ale ads a3:2 be3:0 width1:0 d / c w / r dt / r den rdyrcv blast addr d in invalid addr data out 10 10 t a t d t r t i t i t a t d t r t i t i f_jf030a
preliminar y 4 3 a 80960j d figure 26. burst read and write transactions without wait states, 32-bit bu s addr d d addr data data data data 1 0 1 0 clkin ad31:0 ale ads a3:2 be3:0 width1:0 d / c w / r blast dt / r den rdyrcv t a t d t d t r t a t d t d t d t d t r in in out out out out 00 or 10 01 or 11 00 01 10 11
4 4 preliminar y 80960j d a figure 27. burst write transactions with 2,1,1,1 wait states, 32-bit bu s addr data 1 0 data data data clkin ad31:0 ale ads a3:2 be3:0 width1:0 d / c w / r blast dt / r den rdyrcv t a t w t w t d t w t d t w t d t w t d t r out out out out f_jf032a 0 0 0 1 1 0 1 1
preliminar y 4 5 a 80960j d figure 28. burst read and write transactions without wait states, 8-bit bu s addr d d addr data data data data clkin ad31:0 ale ads a3:2 be 1 /a1 width1:0 d / c w / r blast dt / r den rdyrcv t a t d t d t r t a t d t d t d t d t r 00,01,10 or 11 00,01,10 or 11 00 01 10 11 00 00 be 0 /a0 in in out out out out f_jf033a 00 or 10 01 or 11
4 6 preliminar y 80960j d a figure 29. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bu s addr d d addr data data clkin ad31:0 ale ads a3:2 be 3 / bhe width1:0 d / c w / r blast dt / r den rdyrcv t w t d t d t r t r t a t w t d t d t r 00,01,10, or 11 00,01,10, or 11 t a be 0 / ble be 1 /a1 01 01 0 1 0 1 out out in in f_jf034a
preliminar y 4 7 a 80960j d figure 30. bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian t a t d t r t a t d t r t a t d t r t a t d t r clkin ad31:0 ale ads a3:2 be3:0 width1:0 d / c w / r blast dt / r den rdyrcv 00 00 01 10 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 valid a a a d a d in in d in d in
4 8 preliminar y 80960j d a figure 31. hold/holda waveform for bus arbitratio n clkin valid outputs: ad31:0, ale, al e , ad s , a3:2, be3:0, width/hltd1:0, d / c , w / r , dt / r , de n , blas t , lock hold holda ~ ~ ~ ~ ~ ~ ~ ~ (note) note : hold is sampled on the rising edge of clkin. the processor asserts holda to grant the bus on the same edge in which it recognizes hold if the last state was t i or the last t r of a bus transaction. similarly, valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t i or t r t h t h t i or t a the processor deasserts holda on the same edge in which it recognizes the deassertion of hold.
preliminar y 4 9 a 80960j d figure 32. cold reset wavefo r m c l k i n a l e , a d s , a l e , w / r , r e s e t l o c k / s t e s t v c c d t / r f a i l ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ f i r s t b u s a c t i v i t y ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v a l i d ~ ~ ( o u t p u t ) o n c e a d 3 1 : 0 , a 3 : 2 , d / c w i d t h / h l t d 1 : 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ( n o t e 1 ) ~ ~ ~ ~ i d l e ( n o t e 2 ) h o l d ~ ~ v a l i d i n p u t ( n o t e 3 ) ~ ~ ~ ~ ~ ~ ~ ~ b e 3 : 0 , d e n , b l a s t ~ ~ ~ ~ ~ ~ v a l i d o u t p u t ( n o t e 3 ) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ h o l d a v 1 0 , 0 0 0 c l k i n p e r i o d s , f o r p l l s t a b i l i z a t i o n . c c a n d c l k i n s t a b l e t o r e s e t h i g h , m i n i m u m ~ ~ ~ ~ b u i l t - i n s e l f - t e s t , a p p r o x i m a t e l y 2 0 7 , 0 0 0 c l k i n p e r i o d s ( i f s e l e c t e d ) ( i n p u t ) ~ ~ 1 . t h e p r o c e s s o r a s s e r t s f a i l d u r i n g b u i l t - i n s e l f - t e s t . i f s e l f - t e s t p a s s e s , t h e f a i l p i n i s d e a s s e r t e d . t h e p r o c e s s o r a l s o a s s e r t s f a i l d u r i n g t h e b u s c o n f i d e n c e t e s t . i f t h e b u s c o n f i d e n c e t e s t p a s s e s , f a i l i s d e a s s e r t e d a n d t h e p r o c e s s o r b e g i n s u s e r p r o g r a m e x e c u t i o n . n o t e s : 2 . i f t h e p r o c e s s o r f a i l s b u i l t - i n s e l f - t e s t , i t i n i t i a t e s o n e d u m m y l o a d b u s a c c e s s . t h e l o a d a d d r e s s i n d i c a t e s t h e p o i n t o f s e l f - t e s t f a i l u r e . 3 . s i n c e t h e b u s i s i d l e , h o l d r e q u e s t s a r e h o n o r e d d u r i n g r e s e t a n d b u i l t - i n s e l f - t e s t . ~ ~ ~ ~
5 0 preliminar y 80960j d a figure 33. warm reset wavefor m ~ ~ ~ ~ m a x i m u m r e s e t l o w t o r e s e t s t a t e 4 c l k i n c y c l e s ~ ~ ~ ~ ~ ~ c l k i n a d 3 1 : 0 , a 3 : 2 , d / c s t e s t r e s e t ~ ~ ~ ~ r e s e t h i g h t o f i r s t b u s m i n i m u m r e s e t l o w t i m e 1 5 c l k i n c y c l e s ~ ~ ~ ~ ~ ~ ~ ~ h o l d a ~ ~ ~ ~ ~ ~ ~ ~ v a l i d a l e , a d s , b e 3 : 0 , d e n , b l a s t a l e , w / r , d t / r , b s t a t , w i d t h / h l t d 1 : 0 ~ ~ ~ ~ f a i l ~ ~ ~ ~ ~ ~ h o l d ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ l o c k / o n c e ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ a c t i v i t y , 4 6 c l k i n c y c l e s ~ ~ ~ ~ ~ ~ ~ ~
preliminar y 5 1 a 80960j d figure 34. entering the once stat e c l k i n a l e , a d s , a l e , w / r , r e s e t l o c k / v c c d t / r , w i d t h / h l t d 1 : 0 f a i l ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ o n c e a d 3 1 : 0 , a 3 : 2 , d / c ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ h o l d ~ ~ ~ ~ ~ ~ b e 3 : 0 , d e n , b l a s t ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ h o l d a ~ ~ ~ ~ ( i n p u t ) m i n i m u m 1 0 , 0 0 0 c l k i n p e r i o d s , f o r p l l v c c a n d c l k i n s t a b l e t o r e s e t h i g h , ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ( n o t e 1 ) 1 . o n c e m o d e m a y b e e n t e r e d p r i o r t o t h e r i s i n g e d g e o f r e s e t : o n c e i n p u t i s n o t l a t c h e d u n t i l t h e r i s i n g e d g e o f r e s e t . n o t e s : c l k i n m a y n o t b e a l l o w e d t o f l o a t . ~ ~ ~ ~ s t e s t ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2 . t h e o n c e i n p u t m a y b e r e m o v e d a f t e r t h e p r o c e s s o r e n t e r s o n c e m o d e . ~ ~ s t a b i l i z a t i o n . i t m u s t b e d r i v e n h i g h o r l o w o r c o n t i n u e t o r u n .
5 2 preliminar y 80960j d a table 19. natural boundaries for load and store accesse s data widt h natural boundary (bytes ) byt e 1 short wor d 2 wor d 4 double wor d 8 triple wor d 1 6 quad wor d 1 6 table 20. summary of byte load and store accesse s address offset from natural boundary (in bytes ) accesses on 8-bit bus (width1:0=00 ) accesses on 16 bit bus (width1:0=01 ) accesses on 32 bit bus (width1:0=10 ) +0 (aligned ) ? byte acces s ? byte acces s ? byte acces s table 21. summary of short word load and store accesse s address offset from natural boundary (in bytes ) accesses on 8-bit bus (width1:0=00 ) accesses on 16 bit bus (width1:0=01 ) accesses on 32 bit bus (width1:0=10 ) +0 (aligned ) ? burst of 2 byte s ? short-word acces s ? short-word acces s + 1 ? 2 byte accesse s ? 2 byte accesse s ? 2 byte accesse s
preliminar y 5 3 a 80960j d table 22. summary of n -word load and store accesses ( n = 1, 2, 3, 4 ) address offset from natural boundary in byte s accesses on 8-bit bus (width1:0=00 ) accesses on 16 bit bus (width1:0=01 ) accesses on 32 bit bus (width1:0=10 ) +0 (aligned) ( n =1, 2, 3, 4 ) ? n burst(s) of 4 byte s ? case n =1: burst of 2 short word s ? case n =2: burst of 4 short word s ? case n =3: burst of 4 short words burst of 2 short word s ? case n =4: 2 bursts of 4 short word s ? burst of n word(s ) +1 ( n =1, 2, 3, 4 ) +5 ( n = 2, 3, 4 ) +9 ( n = 3, 4 ) +13 ( n = 3, 4 ) ? byte acces s ? burst of 2 byte s ? n -1 burst(s) of 4 byte s ? byte acces s ? byte acces s ? short-word acces s ? n -1 burst(s) of 2 short word s ? byte acces s ? byte acces s ? short-word acces s ? n -1 word access(es ) ? byte acces s +2 ( n =1, 2, 3, 4 ) +6 ( n = 2, 3, 4 ) +10 ( n = 3, 4 ) +14 ( n = 3, 4 ) ? burst of 2 byte s ? n -1 burst(s) of 4 byte s ? burst of 2 byte s ? short-word acces s ? n -1 burst(s) of 2 short word s ? short-word acces s ? short-word acces s ? n -1 word access(es ) ? short-word acces s +3 ( n =1, 2, 3, 4 ) +7 ( n = 2, 3, 4 ) +11 ( n = 3, 4 ) +15 ( n = 3, 4 ) ? byte acces s ? n -1 burst(s) of 4 byte s ? burst of 2 byte s ? byte acces s ? byte acces s ? n -1 burst(s) of 2 short word s ? short-word acces s ? byte acces s ? byte acces s ? n -1 word access(es ) ? short-word acces s ? byte acces s +4 ( n = 2, 3, 4 ) +8 ( n = 3, 4 ) +12 ( n = 3, 4 ) ? n burst(s) of 4 byte s ? n burst(s) of 2 short word s ? n word access(es )
5 4 preliminar y 80960j d a figure 35. summary of aligned and unaligned accesses (32-bit bus ) 0 4 8 12 16 20 24 0 1 2 3 4 5 6 one double-word short-word load/store word load/store double-word load/store byte, byte accesses short access (aligned) short access (aligned) byte, byte accesses word access (aligned) byte, short, byte, accesses short, short accesses byte, short, byte accesses byte offset word offset one double-word burst (aligned) byte, short, word, byte accesses short, word, short accesses byte, word, short, byte accesses word, word accesses burst (aligned)
preliminar y 5 5 a 80960j d figure 36. summary of aligned and unaligned accesses (32-bit bus) (continued ) 0 4 8 12 16 20 24 0 1 2 3 4 5 6 triple-word load/store quad-word load/store word, word, word accesses word, accesses word, word, word, word, word, word, word accesses byte offset word offset one three-word burst (aligned) byte, short, word, word, byte accesses short accesses short, word, word, byte, word, word, short, byte accesses word, word, word accesses one four-word burst (aligned) byte, short, word, word, word, byte accesses short, word, word, word, short accesses byte, word, word, word, short, byte accesses accesses word, word word,
5 6 preliminar y 80960j d a 6.0 device identificatio n 80960j d processors may be identified electrically according to device type and stepping (see table 2 3 ). the 32-bit identifier is accessible in three ways : ? upon reset, the identifier is placed into the g0 register . ? the identifier may be accessed from supervisor mode at any time by reading the deviceid register at address ff008710h . ? the ieee standard 1149.1 test access port may select the device id register through the idcode instruction . the device and stepping letter is also printed on the top side of the product package . note : this data sheet applies to the 80960j d a and 80960j d a2 steppings . 7.0 revision histor y this data sheet supersedes revision 272596-001. table 2 4 indicates significant changes since the previous revision . table 23. 80960j d die and stepping referenc e device and steppin g version numbe r part numbe r manufacture r x complete id (hex ) 80960j d a, a 2 000 0 1000 1000 0010 000 0 0000 0001 00 1 1 0882001 3 table 24. data sheet version -001 to -002 revision history (sheet 1 of 2 ) table 13, 80960jd dc characteristics (pg. 24 ) removed icc characteristics. added v ol p (output ground bounce) specificatio n table 14, 80960jd icc characteristics (pg. 25 ) new table for comprehensible icc characteristics. added icc?s for reset mode. halt icc for: 80960j d -50 (max) improved from 56 ma to 48 ma, 80960j d -40 (max) improved from 44 ma to 41ma. once icc improved from 30 ma to 10 ma . section 4.5, ac specifications (pg. 26 ) grouped ac specifications tables by frequency. added 40 mhz and 33 mhz ac specifications . table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) section input clock timing s t c s (max) improved from 0.1% to 250 p s table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) section synchronous output timing s t ov 1 (min) improved from 3.0 ns to 3.5 ns. t ov 2 (min) improved from 0.45 t c + 3.0 ns to 0.5 t c + 3.5 ns. t o f (min) improved from 3.0 ns to 3.5 ns. t o f (max) improved from 17 ns to 15 ns .
5 7 preliminar y 80960j d a table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) section synchronous input timing s t is 2 (min) improved from 10 ns to 9 n s table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) section relative output timing s t lx l , t lx a , and t dx d (min) improved from .45 t c - 3 ns to .5 t c - 7.5 ns . table 15, 80960jd ac characteristics (50 mhz) (pg. 26 ) section boundary scan test signal timing s t bs f (max) improved from 8 mhz to .5 t f . t bsis 1 (min) improved from 8 ns to 4 ns. t bsih 1 (min) improved from 10 ns to 6 ns. t bsis 2 (min) improved from 8 ns to 4 ns. t bsih 2 (min) improved from 10 ns to 6 ns . table 24. data sheet version -001 to -002 revision history (sheet 2 of 2 )

▲Up To Search▲

Price & Availability of 80960JD-50

	To Download 80960JD-50 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .